H2 System-On-Chip VHDL based on J1 CPU

H2 System-On-Chip VHDL based on J1 CPU


Category: System on Chip

Created: February 15, 2018

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: Others


The H2 is a System On a Chipc (SoC) built around a stack processor that can directly execute Forth called the H2. The system is written in VHDL and runs on a Spartan 6 board, called the Nexys-3. This CPU is based on the J1 CPU (which was written in Verilog), with extensions and a few difference.

A toolchain is included which can compile a Forth interpreter (eForth) onto the target CPU.

The SoC has several peripherals which include: a timer, a UART, access to the bank of LEDs and switches, an SRAM interface, and an Flash interface, a VGA text mode display accessible via VT100 terminal emulator and a PS/2 keyboard interface.

For those that do not have access to the development board, a simulator written in C is provided. There are actually two simulators, both work under Windows (MinGW) and Linux, one is a graphical simulator using FreeGLUT, the other is purely command line based. They simulate all of the peripherals and offer (nearly) identical behavior to the development boards hardware.

Most files are licensed under the MIT license, some under the LGPL and the Apache license. For more information consult the header for each file.

The project aims to emulate a computer running Forth from the 1980s, and does quite a good job!