Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block

Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block


Category: System controller

Created: December 18, 2014

Updated: January 27, 2020

Language: VHDL

Other project properties

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: B.4

License: LGPL


Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block. Wupper is specifically designed for the 256 bit wide AXI4-Stream interface of the Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe). Wupper has been also successfully ported to Xilinx Kintex UltraScale FPGAs.

DMA read and write

The main purpose of Wupper is therefore to provide an interface to standard FIFOs. This is the done by the DMA_read_write block in the diagram above. The read/write FIFOs have the same width as the Xilinx AXI4-Stream interface (256 bits) and run at 250 MHz. The application side of the FPGA design can simply read or write the FIFOs. Wupper will handle the transfer to Host PC memory, according to the addresses specified in the DMA descriptors.

DMA control

Another functionality of Wupper is thus to manage a set of DMA descriptors. Descriptors consist of an address, a read/write flag, the transfer size (number of 32 bit words) and an enable line. Descriptors are handled by the DMA_control block. These descriptors are mapped as normal PCIe memory or IO registers. Besides the descriptors and the enable line (one per descriptor), a status register for every descriptor is provided in the register map.

Generic register map

Besides DMA specific functions, the DMA control block can also handle generic control and monitor registers for user application.

Interrupt handler

Wupper is provided with a generic MSI-X compatible interrupt controller.

Implementation info

For synthesis and implementation of the cores, it is recommend to use Xilinx Vivado 2014.2. Other IP cores (FIFO, clock wizard and PCIe) are provided in the Xilinx .xci format, as well as the constraints file (.xdc) is in the Vivado 2014.2 Format. Wupper is also known to work well with Vivado 2014.4, constraints will be updated.

For portability reasons, no Xilinx project files will be supplied with Wupper. Instead, a bundle of TCL scripts has been supplied to create a project and import all necessary files, as well as to do the synthesis and implementation. These scripts are be described in details in the /documentation/wupper.pdf distributed with Wupper.


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