SCSI Chip for SRAM Controller and 32 to 8 bits Converter
Category: System controller
Created: September 29, 2008
Updated: January 27, 2020
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
This proyect is designed to adapt either a host system, or a perypherical controller system to a scsi bus.
Also the chip is a DMA controller for a host, in cluding a SRAM controller and a 32 to 8 bits converter for transmit data between a processor and the SCSI bus.
It is formed by 7 submodules that have specific functions that will be explain deeply later in this document.
It can operate in anyone of three posible states : disconected, connected as a target or connected as an Initiator.
The following is a summary of the SCSI protocol between host(initiator) and a target(controller):
- The host selects a SCSI controller
- The controller requests a command from the host specifying the task to be performed. example read disk
- The controller interprets the command and execute it by reading data from the disk and the requesting the host accept the data.
- When al data has been transfered, the controller requests that the host aacept the status byte.
- After the host accepts the status form the controller, the controller disconnects from the bus leaving it free for the next operation.
- Implement full SCSI Features:
- Synchronous Data Transfers un to 4MB/sec
- Can be use as Host adapter or peripheral adapter
- Compliance with ANSI SCSI X3T9.2 specifications
- compatible with most microprocessors through an 8 bit data bus.
- SRAM Controller
- 24 bit data counter.
Signal Descriptions- SCSI interface
The SCSI chip has two different kinds of signals, SCSI bus signals and Processor DMA signals:
- SCSI interface:
- I/O : controls the direction of data movement on the SCSI bus with respect to the initiator. When asserted, data is input to the initiator. I/O is an input signal when the SCSI chip is operating as an initiator, and output signal when is operating as a target.
- MSG_N: is asserted during the message phase, is an input when the chip is operating as an initiator and an output when operating as a target.
- C_N/D : is asserted when there is a control information on the SCSI data bus and de-asserted for data. is an input when the chip is operating as an initiator and an output when operating as a target.
- BSY_N : is asserted by the SCSI chip as an output when attempting to arbitrate for the SCSI bus or when connected as a target. When the chip is conected as an initiator, BSY_N operates as an input.
- SEL_N : The SCSI chip assert it as an out put when trying to select or reselect another SCSI device. The SCSI receives SEL_N as an input when its being selected.
- DBP_N : SCSI bus parity bit.
- DB_N : SCSI bus data bits 0-7
- ATN_N : signals that the initiator has a message to transfer. Is an output signal when the chip is operating as an initiator and an input when connected as a target.
- ACK_N : acknowledges a REQ/ACK data transfer handshake. Is an output signal when the chip is operating as an initiator and an input when connected as a target.
- REQ_N : requests an REQ/ACK data transfer. is an input signal whe the chip is operating as an initiator and an output when operating as a target.
- Processor interface:
- CLK: 10MHz square wave clock.
- DRQ_N/DRQ : interfaces with an external DMA controller and forms the DRQ/DACK handshake for data byte transfers. interfaces with an external buffer. This signal is open drain.
- DACK_N/RCS_N : interfaces with external DMA controller. when asserted, all bus transfers are to or from the data register regardless of the contents of the address register. Interfaces with an external buffer. When is asserted , WE_N and RE_N are enable as outputs.
- INTRQ : signals a local microprocesor or host that a SCSI chip command has terminated or the SCSI interface needs service.
- D : 0-7 Local data bus.
- A0 : is used to access an internal register during the indirect addressing mode operation. A=0 the address of the desired registeris loaded in to the address register during a write cycle.A = 1 the register selected by the address register is accessed
- CS_N : when is asserted , WE_N and RE_N are enable as input signals for accesing registers within the chip.
- WE_N : is an input signal and enables writing to an internal register when used with CS_N. is an output signal and enables writing to the external buffer whenused with RCS_N. is a tri-state signal.
- RE_N : is an input signal and enables reading to an internal register when used with CS_N. is an output signal and enables reading to the external buffer whenused with RCS_N. is a tri-state signal.
- ALE : With the trailing edge of ALE, the address on the local data bus is latched into the address register.
- MR_N : when asserted places the SCSI chip into a disconnect state. All SCSI signals are placed in a passive state.