External Parallel to Internal Wishbone Master Interface Microcontroller

External Parallel to Internal Wishbone Master Interface Microcontroller

Details

Category: System controller

Created: June 22, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

Additional info: Specification done

WishBone compliant: No

WishBone version: n/a

License: GPL

Description

This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller.

The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions are communicating using a wishbone compatible bus within the FPGA.

Features

- 8 bit external interface to a simple parallel port of a regular microcontroller
- two cycle external bus transfers: first address, then data
- interrupt request flag
- bidirectional external data port
- wishbone compatible master interface to connect internal cores

Status

2008-06-23: Specification document available

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