Computer Operating Properly : Watchdog Timer Module

Details
Category: Uncategorized
Created: May 22, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: BSD
Description
The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two specific words to its control registers. The intention of the module is to bring an embedded system back to a “good” state after the software program has lost control of the system.