Simple backtracking 9x9 Sudoku Solver in Verilog

Details
Category: Uncategorized
Created: September 04, 2013
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C implementation of algorithm provided too).
High wiring complexity due to explicit "neighbor" interconnect (row, column, and 3x3 sub-block) may result in unroutable designs on FPGA families with reduced routing resources.
Working on an Zynq XC702 FPGA.