Category: Uncategorized

Created: March 29, 2018

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: Others


VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER)

Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible.
The R6532 integrates several functions:

  • RAM (128 x 8)
  • Two parallel I/O ports
  • Timer functions
  • Interrupt capabilities

These components had very little memory and were often used in groups. For ease of use, RAM has not been integrated in this implementation and will need to be added externally. Only registers, I/O ports, timers and interrupt logic has been implemented.

Signal interface

Note that the data buses are separate (inputs / outputs).

phi2 : The clock signal. Should be connected to the CPU's Phi2 line.
rst_n : The reset signal (negative). Should be connected to the CPU's RST line.
irq_n : The interrupt line (negative). Should be connected to CPU's IRQ or NMI, if needed.
rw_n : The read/write signal (Read = 1, Write = 0). Should be connected to the CPU's R/W line.

cs : Chip select (positive). Should be connected to the address decoding logic.
add[4..0] : Address bus. Should be connected to the CPU's address bus.

din[7..0] : Data bus, inputs. Connected to the CPU data bus outputs.
dout[7..0] : Data bus, outputs. Connected to the CPU data bus inputs (need multiplexers)

pa_in[7..0] : Port A, inputs.
pa_out[7..0] : Port A, outputs.
pb_in[7..0] : Port B, inputs.
pb_out[7..0] : Port B, outputs.

Tests and validation

The R6532 component has been tested on an ALTERA Cyclone IV FPGA - EP4CE6 (and EP4CE10).
It was used in our Gottlieb pinball sound card replacement project, that integrate a 6502 core, RAM, ROM and R6532/R6530 devices.
The board C4E6-K (or C4E10-K) is clocked at 50 MHz, the 6502 core run at 892 Khz.