BRSFmnCE FPGA Implementation

BRSFmnCE FPGA Implementation

Details

Category: Memory Core

Created: August 11, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

This module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several products/projects based on Xilinx Spartan 3AN FPGAs. It can be adapted to other development environments and FPGAs, but only Xilinx ISE and Xilinx Spartan 3A/3AN FPGAs has been used to date.

All components used in this module are inferred, including the Block RAM. This allows the depth and width to be set by parameters. Furthermore, the state of the memory, the write pointer, and FIFO flags can be initialized. This allows FIFO to be preconditioned with a copyright notice, configuration data, etc.

FPGA Implementation Summary

The BRSFmnCE has been used in several projects/products. It is generally used as a deep FIFO for UARTs. The following synthesis and Map/PAR results effectively summarize the resource utilization of the BRSFmnCE in a XC3S200A-4VQG100I FPGA. This FPGA is not the only one in which BRSFmnCE has been used, but it allows the characterization of the resource requirements of the BRSFmnCE.


Number of Occupied Slices: 30
Number of Slice FFs: 35
Number of 4-input LUTs: 32
Number of RAMB16BWE: 1

Reported Speed (Synthesizer): 167 MHz
Reported Speed (MAP/PAR): 187 MHz