SSRAM Interface Memory Core

SSRAM Interface Memory Core


Category: Memory Core

Created: September 25, 2001

Updated: January 27, 2020

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: n/a


The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs.

Core description

Currently 2 designs have been implemented. ssram_conn and cs_ssram.
The entity ssram_conn provides a standard interface to the ssram. It provides the pipeline correction and all IO structures needed for high speed bidirectional data transfers (including full FPGA IO-cell usage).
The entity cs_ssram uses the standard interface to turn the ssram into a cycle shared memory. Because ZBTs feature zero bus latency there is no impact on throughput. Thus providing a low-cost alternative to dual-ported rams.

The design uses attributes to preserve all tri-state enables. Standard compiler strategy is to optimize redundant logic resulting in a single output/tristate enable signal. For maximum performance all output enables have to be preserved. Xilinx and Altera devices (and others probably too) can use their high speed paths to the IO-blocks only if every IO-block has its own output-enable. For ASIC implementations it results in the lowest Tco and Tsu possible.
The attributes used are for Leonardo Spectrum. Please tell me what attributes should be used for other compilers (like synplicity).


- Standard interface for pipelined ZBTs
- Dual ported memory using cycle shared ssram


- Designs are available in VHDL from OpenCores CVS via cvsweb or via cvsget
- ToDo:
- Modify the standard interface so it supports pipelined and flow-through ZBTs
- Modify the standard interface for multi-compiler attributes.
- Modify the cycle shared implementation so it can handle more than 2 sources (tri-ported, quad-ported etc. memories)


Using the slowest Altera APEX20KE device 66MHz is possible.