Generic FIFO in VHDL
Details
Category: Memory Core
Created: June 08, 2014
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.
