Wishbone Wrapper for Xilinx Memory Interface Generator (MIG)

Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback Incrementing Burst Cycle. The second is a non-compliant but streamlined interface developed as a proposal for inclusion as a new Burst Cycle Type geared towards interfacing with high latency devices.