32-bit DDR SDRAM Controller Core

32-bit DDR SDRAM Controller Core

Details

Category: Memory Core

Created: December 20, 2002

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

The ddr_sdr controls read and write access of a programmable
logic device to a single 256 Mbit memory device. The 32-bit
wide user interface basically accepts two commands, read or
write. The control logic initializes the memory after reset
and issues refresh commands from time to time to ensure data
integrity. The data width to the memory device is 16 bits
wide and performs a double data rate operation at 100 MHz
clock rate.

Status

- Version 1.0 available