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Details
Category: Memory Core
Created: Jan 05, 2010
Updated: Jan 27, 2020
Language: Verilog
Other project properties
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This project is to develop a direct mapped cache controller for embedded applications.
Key Design Features
- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush
Synthesis will be conducted using VirtexII Pro
Progress
7th January 2010
Memory(RAM) implementation completed
