Configurable Direct Mapped Cache Controller

Configurable Direct Mapped Cache Controller

Details

Category: Memory Core

Created: January 05, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

This project is to develop a direct mapped cache controller for embedded applications.

Key Design Features

- Direct mapped with configurable address size, line size and number of cache lines
- Non Pipelined architecture
- No Cache flush

Synthesis will be conducted using VirtexII Pro

Progress

7th January 2010
Memory(RAM) implementation completed