DDR3 Synthesizable BFM

DDR3 Synthesizable BFM Click to expand image


Category: Memory Core

Created: November 30, 2011

Updated: November 19, 2019

Language: Verilog

Other project properties

Development Status: Beta

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to run a very high speed. Test shown that is is able to respond to WRITE and READ instruction at 10MHz.


Memory BFM has been tested and passes all Micron DDR3 testbench. It is also has been tested and able to passes Altera DDR3 Testbench.Has been synthesized using Xilinx ISE 13.2 and Quartus II Version 11.1 Build 173