Asynchronous Wishbone Compatible SDRAM Controller

Asynchronous Wishbone Compatible SDRAM Controller

Details

Category: Memory Core

Created: August 01, 2008

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: GPL

Description

SUPERSEDED BY HPDMC.
Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the Milkymist-devel mailing list.