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LinkedinAsynchronous Wishbone Compatible SDRAM Controller
Details
Category: Memory Core
Created: Aug 01, 2008
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
SUPERSEDED BY HPDMC.
Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the Milkymist-devel mailing list.
