Functional RAM Simulation Models

Functional RAM Simulation Models


Category: Memory Core

Created: November 18, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The simu_mem project provides functional simulation models of commercially available RAMs.

Advantages of the simu_mem models

1. Consumes few simulator memory if only few memory locations are accessed because it internally uses a linked list.
2. Simulates quickly because it does not contain timing information. Fast simulator startup time because of the linked list.
3. Usable for any data and address bus width.
4. Works at any clock frequency.
5. Programmed in VHDL.

When the simu_mem models will not be useful
1. When it has to be synthesized.
2. When a timing model is required. Ask your RAM vendor for a timing model.
3. When your design is in Verilog.

Where are the simulation models?

The RAM simulation models are located in rtl/vhdl/. They were tested only with the Modelsim simulator.

How were the models tested?

A testbench exists for ZBT RAMs. sim/rtl_sim/bin/ will execute the simulation. In order to run this test you must replace bench/verilog/samsung/k7n643645m_R03.v with the original simulation file from Samsung. You can find it on the Samsung semiconductor home
page under High Speed SRAM / NtRAM / K7N643645M.

Supported RAM Types

- asynchronous static SRAMs
- synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT RAM)


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