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Details
Category: Memory Core
Created: Mar 31, 2009
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The FIFO implementation outlined in this document can easily be configured to suit the following
- asynchronous FIFO with different clock domains for read and write sides
- synchronous FIFO with programmable flags
- multiple FIFO sharing the same memory resource
This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.
