Versatile FIFO Designs Using Verilog

Versatile FIFO Designs Using Verilog


Category: Memory Core

Created: March 31, 2009

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The FIFO implementation outlined in this document can easily be configured to suit the following

  • asynchronous FIFO with different clock domains for read and write sides
  • synchronous FIFO with programmable flags
  • multiple FIFO sharing the same memory resource

This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.