Single Port ASRAM in VDHL

Single Port ASRAM in VDHL


Category: Memory Core

Created: January 07, 2003

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in VHDL. The main advantage to this verification method is greater stress-test ability and removes the need to create test script language to test the DUT.
The second purpose was to bench-mark the running speed of the ASRAM implemented as three different architectures.
1. Linked-list
2. Bit-vector
3. regular std_logic_vector implementation.


- Demonstrates client-server testbench architecture in VHDL.
- bit-vector array memory core
- standard-logic array memory core
- dynamic linked-list memory core.