Configurable Cordic Core in Verilog
Details
Category: Arithmetic Core
Created: September 14, 2008
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details. Source and user manual available here
Status
- Tested in hardware
