Number Sorting Device O (N)

Details
Category: Arithmetic Core
Created: April 13, 2014
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
// number sorting device, sequential, 2*N clocks for N
// linear buffer implementation
// sequential, stable, can be partly readed, decreasing order
// reset is not implemented
// see sort_stack_algorithm.png to catch the idea
// number sorting, tree-like implementation, sequential,
// energy efficient (theoreticaly)
// see sort_tree_algorithm.png to catch the idea
Article(Russian): http://habrahabr.ru/post/222287