128-bit Pseudo Random Number Generator Using LFSR
Details
Category: Arithmetic Core
Created: August 23, 2018
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Alpha
Additional info: FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This PRNG uses Fibonacci LFSRs with a estimated period of 3.40282366920938463463374607431768211455 × 10^38 clock cycles Expression: X^128 + X^126 + X^101 + X^99 + 1
Avaible at:
https://github.com/rodrigowue128bit-prng
