Facebook
Google
GitHub
LinkedinEfficient Floating Point Logarithm Unit for FPGAs
Details
Category: Arithmetic Core
Created: Jan 05, 2010
Updated: Jan 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs.
The unit is an implementation of the ICSILog algorithm.
