Anti-Logarithm (square-root), Base-2, Single-cycle
Click to expand image
Details
Category: Arithmetic Core
Created: August 08, 2010
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
A fast (single-cycle) base-2 antilog function.
Doesn't run quite as fast as the Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.
To do a single-cycle square-root, first take the log. Then, divide that result by 2 (shift), and take the antilog. Tada...
