Hardware Implementation Of Binary Fully Digital Phase Locked Loop
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Details
Category: Arithmetic Core
Created: March 30, 2011
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This project is a hardware implementation of a Binary Fully Digital Phase Locked Loop. The loop performance is analyzed theoretically, experimentally, and by computer simulation in the presence of random Gaussian phase jitter.
