Recent advances in communications and networking technologies have made it possible that many applications use digital videos such as teleconferencing and multimedia communications. These applications require a very large bit-rate if being handled without compression. Most video compression standards such as HDTV, H.261, JPEG and MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.
Discrete Cosine Transform is decomposing the signal into weighted sums of cosine harmonics; unlike DCT, Discrete Fourier Transform decomposes the signal into weighted sums of orthogonal sines and cosines that when added together reproduce the original signal.
FreeDCT-L is a low power architecture 1-Dimensional 8-point DCT/IDCT core that occupies minimal area for systems that do not require high-speed operation (e.g. Still Image Compression in digital cameras, Audio compression applications). The core’s operating resolution can be easily controlled. The main goal of designing the core was to minimize the size and power consumption. It uses about 3000 gates when implemented on FPGAs. After implementing the design using Alliance Series software for Xilinx XC4000E FPGA family, timing simulation results showed that the core can operate at a speed of 29 MHz. When implementing the design on ASIC 0.8-micron technology, timing simulation showed that the core will operate at a maximum frequency of 51 MHz. The core occupied an area of 1.1 mm2 and contains 11,162 transistors.
FreeDCT-M is a moderate speed 1-Dimensional IDCT core. It processes 12-bit words at a rate of 1 bit per clock cycle. The core will be suitable for MPEG decoding/encoding at the MP@ML ( Main Profile / Main Level). The VHDL core associated with detailed explanation and documentation will be released later.
Both cores associated with documentation are packed here in a ZIP file, please feel free to send your opinions or suggestions regarding my work