32-bit Fixed Point Square Root (Recursive Algorithm)

32-bit Fixed Point Square Root (Recursive Algorithm)


Category: Arithmetic Core

Created: March 13, 2015

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined with Initiation Interval of 1 clock cycle, and it perform the computation of a single square root with a latency of 3 clock cycles.
The design has been tested on 45nm ASIC library.