Suslik Scalar Risc CPU

Suslik Scalar Risc CPU


Category: Arithmetic Core

Created: August 04, 2015

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: BSD


Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative 16kb code & data cache(separate). It also has compare-and-jump instruction and lacks condition flags.