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Suslik Scalar Risc CPU

Suslik Scalar Risc CPU

Details

Category: Arithmetic Core

Created: Aug 04, 2015

Updated: Jan 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: BSD

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Description

Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative 16kb code & data cache(separate). It also has compare-and-jump instruction and lacks condition flags.

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