Free and open source double precision Floating Point Unit (FPU).
The openFPU64 currently features:
- double precision
- rounding (to nearest even)
- validated against IEEE754
- Compatible with Avalon Bus
- Wishbone interface will be provided soon
New algorithms can be added easily, just modify the code marked
Everything marked with FUTURE is not yet implemented,
but already added for easier transition.
Tested on CycloneII and Cyclone III FPGAs.
If any questions arise, don't hesitate to contact me.
Add/Sub have an fmax of 112Mhz on a Cyclone II.
Multiply has a fmax of 70Mhz on a Cyclone II.
A faster implementation of Multiply will be provided soon.
(faster in regard to fmax, with only 2 clock cycles more delay)
Due to the size and a 'bug' in the websvn which got the tar.bz2 corrupted I removed the testsuites from svn.
I uploaded them to
please download them from there.
After downloading them, untar them to tests/
From openfpu64 root directory you can now create the testsuites using
You can then compile the openfpu64_tb.vhd with modelsim or ghdl.
If you use ghdl you can generate the executable testbench by simply running make.
The testsuites contain 45k testcases for add/sub each and 90k for multiply.