CAVLC Decoder Architecture Parsing Process in ITU-T H.264

This IP implements the CAVLC parsing process in ITU-T H.264 (05/2003)

Features

- Compatible with ITU-T H.264 (05/2003), but it do not calculate nC and store TotalCoeff,
you need to add a nC_decoder outside this core.

- New structure for run_before decoder, the core doesn't save Runs in flip-flops and
doesn't need the run_combine process, this feature reduces both cycle and resource.

- this core has a simple interface

- 9 cycles per cavlc block on average(including P frames)

- Fully synchronous design, Fully synthesisable

Status

Documentation

Synthesis results

Push-button synthesis results for various targets.

Altera:
- Cyclone EP3C55F256C6 : 1085 LEs @ 114MHz
- Stratix EP2S15F484C3 : 939 LUTs @ 128MHz

Xilinx:
- Virtex XC4V1X200FF1513-10 : 1467 LUTs @ 96MHz