CAVLC Decoder Architecture Parsing Process in ITU-T H.264

CAVLC Decoder Architecture Parsing Process in ITU-T H.264


Category: Arithmetic Core

Created: October 21, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Beta

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


This IP implements the CAVLC parsing process in ITU-T H.264 (05/2003)


- Compatible with ITU-T H.264 (05/2003), but it do not calculate nC and store TotalCoeff,
you need to add a nC_decoder outside this core.

- New structure for run_before decoder, the core doesn't save Runs in flip-flops and
doesn't need the run_combine process, this feature reduces both cycle and resource.

- this core has a simple interface

- 9 cycles per cavlc block on average(including P frames)

- Fully synchronous design, Fully synthesisable



Synthesis results

Push-button synthesis results for various targets.

- Cyclone EP3C55F256C6 : 1085 LEs @ 114MHz
- Stratix EP2S15F484C3 : 939 LUTs @ 128MHz

- Virtex XC4V1X200FF1513-10 : 1467 LUTs @ 96MHz