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IP Cores

Hardware Load Balancer for Multi-Stage Software Router

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  • Hardware Load Balancer for Multi-Stage Software Router

Hardware Load Balancer for Multi-Stage Software Router

Hardware Load Balancer for Multi-Stage Software Router

Details

Category: Arithmetic Core

Created: September 27, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: LGPL

Download Core Submit Issue

Description

n/a

Related IP Cores

  • 32-bit Signed Integer Divider
  • Fully Tate Bilinear Pairing Core in Verilog 2001 for FPGAs
  • 32-bit Pipelined 5x4Gbps CRC Generator
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