MESI Coherency InterSection Controller

MESI Coherency InterSection Controller


Category: Arithmetic Core

Created: January 02, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It synchronizes the memory requests of the system masters. It enables to keep the consistency of the data in the memory and in the local caches. This project provides the following elements:

  1. A synthesizable controller core with a complete environment of verification, synthesis, and documentation.
  2. Instructions for integrating MESI_ISC to a system.
  3. A definition and requirements of the system masters.

MESI_ISC Specification (ver 0.12)


  • Documentation: On progress. Main chapters have written.
  • RTL: Done.
  • Verification: On progress. A basic test plan has done.
  • Synthesis: On progress. Initial synthesis has passed successfully.


A schematic diagram of a coherency system with MESI_ISC:

Project's Environment Structure

The full environment of the project can be downloaded here. The following drawing describes the directories structure of the environment.