Category: Arithmetic Core

Created: March 06, 2015

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


Arithmetic core originally created by:

Cesar, Julio
Fernandes, Felipe



This file is part of the APB to I2C project


Description & License

Implementation of APB IP core according to crcahb IP core specification document.

To Do: Things are right here but always all block can suffer changes


Copyright (C) 2009 Authors and OPENCORES.ORG


This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains  the original copyright notice and the associated disclaimer.

This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General

Public License as published by the Free Software Foundation;

either version 2.1 of the License, or (at your option) any later version.


This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.


You should have received a copy of the GNU Lesser General Public License along with this source; if not, download it