Single Clock Unsigned Division Algorithm

Single Clock Unsigned Division Algorithm

Details

Category: Arithmetic Core

Created: April 23, 2004

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, Specification done

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

Before You Read

This is a brief overview of the article about single-clock unsigned integer division algorithm. For comparison and estimation of proposed algorithms please refer to the full article... (see PDF file from downloads).

Overview

Now two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during one clock. However there are no principle objections against getting all digits of the quotient and the remainder during one clock. So the author tried to develop such kind of algorithm.

Links

These cores are developed and provided by ASIC reseach department Leader of DeverSYS Corp., Vladimir V.Erokhin. More useful fundamental (and not only) FREE IP Cores can be found at DeverSYS web www.deversys.com.

Methodology (brief)

Restoring algorithm is seemed to be sequential in nature because during remainder restoring there is positive feedback (A=A – B + B at the same cycle). To avoid the feedback it is necessary to insert register for intermediate result storing. Thus, non-restoring algorithm was chosen as basic for one-clock division algorithm.

Recursive approach was chosen due to it provides compact and transparent description. It is easy to see that synthesis result of the description is sequence of adders.