2D FHT - Two Dimensional Fast Hartley Transform

Details
Category: Arithmetic Core
Created: May 01, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points.
Presented algorithm is FHT with decimation in frequency domain.
Main Features
- High Clock Speed
,
- Low Latency(97 clock cycles)
,
- Low Slice Count
,
- Single Clock Cycle per sample operation
,
- Fully synchronous core with positive edge triggering
,
- Flexible core control with regard to input data width
,
,
,
,
,Functional Description,
,
,,
,
,,
,
,
,Block Diagram,
,,
,
,Verification,
,
,
,
,Implementation Result,
,
Xilinx FPGA | Slices | DSP48 | BRAM | Freq., MHz |
---|---|---|---|---|
Virtex-4 xc4vlx60 | 818 | 4 | 1 | 200 |
,
,
,
,
Status
RTL Verilog release of the Two Dimensional Fast Hartley Transform Algorithm.
Verilog RTL - 1st version released. Refer to repository for latest revision.
Verification - If you have any question please feel free to send me message.
Testbench - If you have any question please feel free to send me message.
Documentation - If you have any question please feel free to send me message.