2D FHT - Two Dimensional Fast Hartley Transform

RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points.
Presented algorithm is FHT with decimation in frequency domain.

Main Features

• High Clock Speed

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• Low Latency(97 clock cycles)

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• Low Slice Count

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• Single Clock Cycle per sample operation

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• Fully synchronous core with positive edge triggering

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• Flexible core control with regard to input data width

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,Functional Description,
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,Block Diagram,
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,Implementation Result,
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Xilinx FPGA	Slices	DSP48	BRAM	Freq., MHz
Virtex-4 xc4vlx60	818	4	1	200

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Status

RTL Verilog release of the Two Dimensional Fast Hartley Transform Algorithm.
Verilog RTL - 1st version released. Refer to repository for latest revision.
Verification - If you have any question please feel free to send me message.
Testbench - If you have any question please feel free to send me message.
Documentation - If you have any question please feel free to send me message.