Booth Array Multiplier for Xilinx FPGAs
Details
Category: Arithmetic Core
Created: October 17, 2017
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This IP core provides a resource efficient implementation of a Booth Array Multiplier for Xilinx FPGAs as proposed in:
M. Kumm, S. Abbas, and P. Zipf, An Efficient Softcore Multiplier Architecture for Xilinx FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2015, pp. 18–25
