Viterbi HDL Code Generator

Viterbi HDL Code Generator


Category: Arithmetic Core

Created: May 27, 2004

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Beta

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: GPL



- direct traceback option.
- self test automation
- support any popular convolution code.
- throughput and area of decoder are scalable.
- in place state metric storage.
- parameterized modules.
- something else.


- Place a VHDL/Verilog version for K=7 rate=1/2 Poly=(91,121 in decimal) TracebackDepth=64 decoder for Download
  It's a zip file, rename to .zip or look up the example section.
- Version 1.3
- Place a TD-SCDMA version of K=9 rate=1/2 decoder for download.
- Place a VHDL version of K=9 rate=1/2 decoder for download, in the requirement of Mitchell.
- Version 1.2
- contributed by moti: add, new testbench, insert srst signal in traceback module
- Version 1.1
- Version 1.0
- To be continued
- Updated

Viterbi HDL Code Generator

This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications. If you have any advices, please email to And I have creat a project at, too. You can find them here. Now you can post questions (Disabled)