Configurable Parallel Scrambler Descrambler

Configurable Parallel Scrambler Descrambler


Category: Arithmetic Core

Created: July 29, 2014

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a behavioral module for parallel scrambler/descrambler.
There are RTL scrambler modules available, the purpose of this project is to built a code that is easier to understand and more flexible for reconfiguration. The code is synthesize-able, and should not cost more than RTL modules.