Fixed Point Arithmetic Modules Verilog

Fixed Point Arithmetic Modules Verilog


Category: Arithmetic Core

Created: August 25, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


This project was started in order to create fixed point (Q format) arithmetic modules in verilog.

What was created was a parameterized (specify size (N) and number of fractional bits (Q)) implementation to make configuring for different projects simple.

This implementation uses the following data structure:

| sign (0+/1-) | whole number | fractional bits |
| ____1 bit___ | _N-Q-1 bits_ | _____Q bits____ |

The following modules were created:
-Twos Complement
-Addition (Combinational)
-Multiplication (Combinational using standard * operator)
-Division (Clocked, standard binary division)

Each of these modules is accompanied by a testfixture, and each has been tested for minimal functionality

NOTE: Division's testfixture (qdiv_tf.v) contains 2 tasks that convert between verilog real and fixed point representations (including checking for numbers too big to represent and loss of precision).

SVN Files

The source files in the SVN have been separated into three groups:

- src: containing the verilog sources files {qadd.v,qmult.v,qdiv.v,qtwosComp.v}. These are the parameterized verilog modules implementing the fixed point arithmetic

- testfixtures: containing the three testfixtures for each of the arithmetic operations (add,mult,div). These testfixtures show how data is being entered into the data structure from real life (giving understanding to the user in how to implement in their own projects).

- implementation: containing a sample 'top' module that implements the arithmetic operations in a Q23/32bit scenario