Pipelined FFT/IFFT 256 Points Processor

Pipelined FFT/IFFT 256 Points Processor


Category: DSP Core

Created: February 01, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


Pipelined FFT/IFFT 256 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 256 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.

Main Features:

  • 256 -point radix-8 FFT
  • Forward and inverse FFT.
  • Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 580 clock cycles (839 clock cycles when the direct output data order), simultaneous loading/downloading supported
  • Input data, output data, and coefficient widths are parametrizable in range 8 to 16
  • Two and three data buffers are selected.
  • FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at 250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle, respectively.
  • FFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1652 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 670 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.
  • Overflow detectors of intermediate and resulting data are present.
  • Two normalizing shifter stages provide the optimum data magnitude bandwidth.
  • Structure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.
  • Can be used in OFDM modems, software defined radio, multichannel coding.

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