OpenCores54x 16/32, Dual 16-bit DSP Core

OpenCores54x 16/32, Dual 16-bit DSP Core


Category: Processor

Created: April 08, 2002

Updated: January 27, 2020

Other project properties

Development Status: Beta

WishBone compliant: Yes

WishBone version: n/a

License: n/a


The OpenCores54x (OC54x) DSP core is a cleanroom implementation of a popular family of DSPs designed by the No.1 DSP supplier from the southern part of the US.

The core is designed to be software compliant with the original Texas Instruments C54x DSP. However, the core is not designed to be 100% compatible with the TI's C54x chips. The core features some extension and improvements over the original design, which make it not-compatible. Also, partially caused by the structure choosen, partially to not completely compete with TI, some operating modes and hence opcodes are not supported. See the compatibility section for more detailes.


- 16/32, dual-16 bit DSP core
- 4 Wishbone compliant external busses
- highly pipelined for high performance
- Up to 5 operations per cycle
- structural & opcode compatible with TI's C54x family of DSPs
- First synthesis results: >40MHz in FPGA, >300MHz in .18u


- Barrel Shifter
- Compare Select Store Unit (CSSU)
- Auxiliary Register Arithmetic Unit (ARAU)

- Data Address Generator
- Program Address Generator
- Instruction Decoder


- Texas Instruments C54x Code Composer Studio or C54x compiler/assembler/linker
- GCC (GNU binutils 2.11 and later). Use tic54x as the target (--target=tic54x)


Listed below are known issues between this implementation and Texas Instruments C54x DSPs.

- CMPT is not supported.
The compatibility bit is not supported. As a result ARP is always set to zero.
- EDB is 32bits wide,
The EB data bus is 32bits wide to support single cycle 32bit write accesses. Long words are always written in 1 cycle. In contrast to the C54x there's no difference between even and odd word addresses. The MSB is always written at the higher address.