RISE Microprocessor Pipelined 16-bit RISC processor

RISE (Rarest Instruction Set Ever) is a pipelined 16-bit RISC processor with a simple instruction set. One outstanding feature of the instruction set is that all instructions are conditional, i.e. the execution of a instruction may depend on flags in the status register. The processor is equipped with 16 registers: 12 general purpose registers and 4 registers that have are reserved for specific functions (e.g. program counter). The HDL used for this project is VHDL. For further information on the instruction set architecture have a look at this page:

http://en.wikiversity.org/wiki/Computer_Architecture_Lab/Winter2006/LechnerWalterStadlerTrinklWorkplace

Features

- 16-bit RISC CPU
- 16 registers
- Leightweight but powerful ISA
- Conditional instructions
- Pipelined: 5 stages

Status

- Beginning of development phase