MicroSimplez Didactic Processor

MicroSimplez Didactic Processor


Category: Processor

Created: March 09, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows
simulate and synthetize the Simplez processor. It is a didactic processor created by
Gregorio Fernández in his book "Conceptos Básicos de Arquitectura y Sistemas Operativos",
2003 Edition.

This theoretical processor has a von Neuman architecture, with a set of eight instructions
and 512 memory words. Each twelve bits word, contains two fields: operation code and
data address. Basically, Simplez repeats cyclically the next three steps:

- Reads the instruction stored in a main memory's address.
- Decodes the instruction and executes it.
- Generates the address in the main memory of the next instruction.