Graphics Accelerator with Bresenham Line Drawing Algorithm

Graphics Accelerator with Bresenham Line Drawing Algorithm


Category: Video Controller

Created: May 16, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


This project is a group of hardware units that perform graphics algorithms.
For testing purposes, beside the Units that perform these algorithms, there is a Frame Buffer that holds the image drawn and a Video Controller that outputs the image to a screen. In addition to the user interface which consists of switches and push buttons that selects the color, position, function performed, .. etc.

Current State

Till now we have the Bresenham Line Drawing Algorithm.
Due to the Limitations of the FPGA that I am working on, the Frame Buffer is only 170x120 pixels x 8 Colors.


This video shows a test for using the current project where I write my name using Lines with different colors.