A New Technique Utilizing Carbon Nanotube Transistors Aims for More Energy-Efficient 3D Microprocessors

This swift production has been achieved by using the same equipment used to manufacture silicon-based transistors. Carbon nanotube field-effect transistors (CNFETs) are more energy-efficient than current silicon chips and could be used to build new types of three-dimensional processors, however, they have until now mostly existed in a limited space due to manufacturing constraints. 

Now, MIT researchers have demonstrated how CNFETs can be fabricated in large quantities on 200 mm wafers, the industry-standard in chip design, using existing silicon manufacturing facilities, and semiconductor foundries. 

 

Carbon Nanotube Field-Effect Transistors

Although technical advances have been bringing the price of silicon-based transistor manufacturing down for decades, this trend is fast approaching its end with the realization of Moore’s Law and the fact that we are no longer seeing energy efficiencies increase as more transistors are crammed into integrated circuits. 

CNFETS, on the other hand, are far more energy-efficient than silicon-based transistors, “an order of magnitude more… efficient” according to Max Shulaker who led the MIT team’s research. Unlike silicon-based transistors that are made at temperatures around 500 degrees Celsius,

CNFETs can be produced at near-room temperatures. "This means that you can actually build layers of circuits right on top of previously fabricated layers of circuits, to create a three-dimensional chip," Shulaker explains. "You can't do this with silicon-based technology, because you would melt the layers underneath." Such 3D computer chips made from CNFETs are expected to beat the performance of state-of-the-art 2D chips made from silicon by combining logic and memory functions.

 

MIT researchers Anthony Ratkovich, left, and Mindy D. Bishop, holding an example of a silicon wafer. Image credited to MIT

 

Fabricating CNFETs

CNFETs can be fabricated using various methods, however, one of the most effective ways to deposit nanotubes is called incubation. This method involves submerging a wafer in a bath of nanotubes until they stick to the wafer’s surface. 

Although the incubation method is practical for industry, this doesn’t align the nanotubes in a way that leads to ideal performance levels, which is dictated in large part by the deposition process. Nanotubes either stick to the wafer in random orientations or in the same direction, the latter being ideal but difficult to achieve. "It's really hard to lay down billions of tiny 1-nanometer diameter nanotubes in a perfect orientation across a large 200-millimeter wafer," Mindy Bishop, a PhD student in the Harvard-MIT Health Sciences and Technology program, explains. "To put these length scales into context, it's like trying to cover the entire state of New Hampshire in perfectly oriented dry spaghetti."

Following experiments, Bishop and the research team were able to conclude that the simple incubation process would work to produce a CNFET that could outperform silicon. 

 

1,100 Times Faster

Careful observations of the incubation process showed the researchers how they could alter it to make it more viable for industry. For example, they found that dry cycling, a method of intermittently drying out the submerged wafer, could reduce incubation time from two days to 150 seconds. 

After looking at the deposition technique used to make the CNFETs, Shulaker and colleagues made some changes to speed up the fabrication process by more than 1,100 times when compared to the conventional method while simultaneously reducing production costs. Their technique deposited CNTs edge-to-edge on the wafers. 

Shulaker said that his study represents "a giant step forward, to make that leap into production-level facilities." Bridging the gap between lab and industry is something that researchers "don't often get a chance to do," he adds. "But it's an important litmus test for emerging technologies."

The next step for the research team will be to build different types of integrated circuits out of CNFETs in an industrial setting and explore some of the new functions that a 3D chip could offer.