Andes and Green Hills Collab Yields RISC-V-based SoC for Automotive Safety

August 30, 2022 by Abdulwaliy Oyekunle

The two companies intend to introduce advanced safety functionalities via RISC-V to target use cases in the automotive industry.

Manufacturers in the computing industry use RISC-V to create custom designs in RISC-V processor-based architectures. Andes Technology is one such company introducing safe and secure computing on its AndesCore 25-Series 32/64-bit CPU IP cores.

Having previously received the ISO 26262 safety certification, Andes Technology aims to up its game in the computing industry by collaborating with Green Hills to produce market-leading 32/64-bit RISC-V-based SoCs that meet the safety requirements of automobile electrical and electronic systems.


Close-up view of Andes Technology’s products

Close-up view of Andes Technology’s products. Image used courtesy of Andes Technology


In this latest collaboration, the two companies are employing hardware and software solutions to create an integrated AndesCore family of processors that are capable of handling the safety requirements of vehicle electronic control units (ECUs) while reducing the cost and development time for developers.


AndesCore Processors

The AndesCore processors from Andes Technology include several 32-bit/64-bit CPU cores based on the AndeStar V5 instruction set architecture (ISA). The company employed the AndesCore 25-series processors, including the N(X)25F, D25F, A(X)25, and A(X)25MP CPU IP cores in the automotive safety RISC-V-based SoC product. 

In addition to floating-point extensions, the 25-series processors are equipped with a 5-stage pipeline that is optimized for high operating frequency and high performance. They also feature instruction and data caches, local memories for low-latency accesses, and ECC for L1 memory soft error protection. The processors also provide branch prediction for efficient branch execution. Users can control power and energy consumption from multiple power management settings.

The A(X)25MP block diagram

The A(X)25MP block diagram. Image used courtesy of Andes Technology


One of the processors in the series, the A(X)25MP, has a single instruction multiple data (SIMD) ISA that is said to accelerate performance in voice, audio, image, and signal processing. According to the company, the processors in the series have ISO 26262 safety certification. 


µ-velOSity RTOS

The µ-velOSity real-time operating system (RTOS) from Green Hills is a software solution written in the C programming language. The software is compatible with the RISC-V-based AndeStar V5 architecture. According to Green Hills, the operating system offers a clear and concise application programming interface (API) that shortens the development cycle. Kernel features supported in the RTOS include resource allocation. TCP/IP, MS/DOS, USB device/mass storage class, and embedded graphics. 

µ-velOSity can be used in on-chip memory, providing users with a faster execution speed and eliminating the need for off-chip memory. Faster execution speed together with quick boot time makes the software a useful solution in automotive applications.  

The software is equipped with several development tools to aid designers. These development tools include optimizing compilers, the MULTI-integrated development environment, and hardware debug devices such as the Green Hills Probe. According to the company, µ-velOSity RTOS is ASIL certified.


Green Hills Probe V4

The Green Hills Probe V4 is a joint test action group (JTAG) that provides up to 4 GB of high-speed trace memory to enable software developers to debug, optimize, and test trace connections. It can be used in conjunction with the TimeMachine Debugging Suite from Green Hills.

One unique feature of the JTAG probe V4 is that it can efficiently detect and find bugs called "Heisenbugs." Heisenbugs are bugs that disappear or don’t reproduce while debugging. The probe utilizes a trace capture mechanism to find the bugs that are responsible for software and product delays.

Green Hills says the probe supports the latest high-speed serial trace (HSST) protocols. It also features JTAG clocks from 2.5 kHz to 120 MHz with nearly 100% data payload utilization to maximize the download speed of target processors such as AndesCore processors. The trace architectures supported by the probe include RISC-V, Intel MIPI, and Arm CoreSight, among others.


The JTAG Probe V4

The JTAG Probe V4. Image used courtesy of Green Hills Software


Commenting on the hardware-software automotive safety solution, Dan Mender, VP of Green Hills' business development, remarked that SoC providers utilizing the AndesCore 25-Series family can immediately start developing their next-generation vehicle ECUs with the high-performing, low-power offerings. These integrated solutions, he says, may reduce customers’ time to market and development costs.