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CHIPS Alliance Brings Powerful Players into Open Source Hardware Collaboration

July 08, 2019 by Gary Elinoff

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

Linux changed the world with its open approach to operating systems. The Linux Foundation has now partnered with a new initiative, CHIPS Alliance, to bring the same open source ethos to hardware design.

All About Circuits had a chance to speak to Ted Marena, Interim Director of CHIPS Alliance, about CHIPS Alliance, its mission, and its inaugural event this June, which was hosted by Linux, itself.

What Is CHIPS Alliance?

The mission of the CHIPS Alliance is, in its own words, “to harnesses the energy of open source collaboration to accelerate hardware development”. The acronym “CHIPS” breaks down to Common Hardware for Interfaces, Processors, and Systems.

It is expected that by “creating an open and collaborative environment,” CHIPS Alliance can hope to slash development costs for everyone. A major goal is for many to work together to develop open source designs for devices like CPUs, as well as other blocks of complex intellectual property. The collaboration will also give rise to open source hardware and software tools.

The board of directors for the organization includes Western Digital, Google, Esperanto Technologies, and SiFive—other full members include Antmicro, Imperas Software, and Metrics Technologies.

Marena explains it like this: "What CHIPS Alliance does is collaboratively create hardware and open source development tools for the masses. The idea is, instead of each individual company having to make a processor or embedded controller, we all collaborate together. Make one, verify it, validate it, put it on the shelf, and then—whenever we need it—we just go and grab it."

After all, why should everyone, Marena argues, make their own designs separately?

"We want to harness the energy of the open source community for hardware as it has done for Linux and other software," Marena says.

 

"We want to harness the energy of the open source community for hardware as it has done for Linux and other software."

 

As Dr. Yunsup Leeco-founder and CTO, SiFive decries, “Semiconductor design starts have evaporated due to the skyrocketing cost of building a custom SoC. A healthy, vibrant semiconductor industry needs a significant number of design starts, and the CHIPS Alliance will fill this need.”

Google, too, has signed up for the cause. According to Google Cloud's Senior Director of Technical Infrastructure, Dr. Amir Salek, “We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. Google is committed to fostering an open community of collaboration and innovation in both hardware and software. The CHIPS Alliance will provide the support and framework needed to nurture a vibrant open source hardware ecosystem for high-quality, well-verified and documented components to accelerate and simplify chip design.”

The Open-Source Umbrella

In discussing the CHIPS Alliance, it is useful to discuss that entity’s relationship to the RISC-V Foundation and to the Linux Foundation.

Zvonmir Bandic is the Senior Director of HW platforms at Western Digital, Chairman of the CHIPS Alliance, and a member of the board of the RISC-V Foundation. As Bandic describes it in an online podcast, the CHIPS Alliance is a ”hardware equivalent to the Linux operating system movement”. 

This is not quite the same thing as RISC-V, which concerns itself with the interfaces between software and hardware (as opposed to hardware, itself). Bandic points out that the CHIPS Alliance and RISC-V both operate under the umbrella of the Linux Foundation.

 

Early CHIPS Alliance supporters. Image from Chips Alliance

But Why Would I Want to Share My IP?

The million-dollar question. Here, Bandic outlines a typical scenario. Two or more companies have huge amounts of valuable data and they want to start data mining projects, and they are unsatisfied with the effectiveness or cost of what’s available commercially. They can work together on chip-level components for machine learning and split the HW cost, then go their separate ways to do their respective data mining.

They have exactly the device they need, and they’ll pay no cost for the IP.

What Bandic left out was the obvious result that if the chip proves successful, both organizations can expect to reap the monetary rewards to be gained in teaching others how to use the new, hot, open-source chip. Many a fortune has been made in the various aspects of Linux support.

Marena says that there is some resistance to the idea of IP sharing, a "hurdle that some people have to get over," if you will. But, he says, there are good reasons to join in. "A lot of people are starting to come around," he says, citing the example of a custom controller that doesn't need to be IP-protected: "That controller that nobody sees but your development team—there's nothing super magic about these things. So secret sauce is really a particular interface or how you accelerate a particular piece of data or what have you. CHIPS Alliance doesn't go into that, rather focusing on the standard building blocks or the peripherals that are industry standard."

Initial Open Source Contributions

Google has made available its Universal Verification Methodology (UVM)-Based Stream Generator Environment for RISC-V Cores. This environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.

Western Digital is planning to contribute its 9-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV Instruction set simulator. Additional contributions will include specification and early implementations of OmniXtend cache coherence protocol.

It is expected that initial projects will be focused around RISC-V compute cores, design tools, and design verification methodologies. Important advances in areas such as multi RISC-V core, Linux capable based SoCs and CPUs will also be sought.

The First Meeting of the CHIPS Alliance

Under the auspices of the Linux Foundation, CHIPS Alliance held its first one-day workshop on June 19, 2019 at Google’s offices in San Jose California. The location alone speaks volumes about the scope of this endeavor and of its potential. Getting right down to business, forums were held where actual RTL (register-transfer level) design proposals were discussed.

The Workshop

The outline of the workshop, presented by the Linux Foundation prior to the event, is available here.

The first thing the reader will notice is that the topmost menu bar is dominated by links to various Linux Foundation events. This underscores the fact that the CHIPS Alliance is a functioning entity under the Linux Foundation’s broad umbrella. Indeed, it will be noticed that, as might be expected, there is a very blurry line separating the concerns of the RISC-V Foundation and the CHIPS Alliance.

 

 

The web directory for the recent show, which took place on June 19, 2019, can be found here.

Workshop Agenda

Here are some highlights of the event, representing a :

  • Why Open Source Hardware Unlocks Innovation – Martin Fink, EVP and CTO at Western Digital
  • Vision for Open Source Hardware Developments – Amir Salek, Senior Director of Engineering at Google
  • SweRVCore: Western Digital’s First RISC-V Core – Zvonimir Bandic, Senior Director at Western Digital
  • A Natural Fit, RISC-V with CHIPS Alliance – Naveed Sherwani – President and CEO of SiFive

The complete list of talks give at the show is available here.

Other Open RISC-V Initiatives

SiFive's TileLink open memory bus is working in partnership with Western Digital's OmniXtend memory fabric to allow sharable memory over the Ethernet. 

According to Marena, "Because [RISC-V] is open and because we can pick whatever we want, we chose to send it over Ethernet. A number of devices can use Ethernet to share main memory, which has never happened before because, previously, the processor always 'owned' that main memory... This ability to share memory now in a totally new way was made possible because of the openness that RISC-V afforded."

The effects of such a system are far-reaching, says Marena, in terms of structuring memory. "For a data center, this would be a whole new way to architect a system."

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