Microchip Announces First RISC-V-based SoC FPGA to Use Half the Power of Other FPGAs

December 10, 2019 by Lisa Boneta

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

Microchip recently announced the Early Access Program (EAP) for their low-power, RISC-V-enabled PolarFire SoC family, based on their award-winning PolarFire FPGA family. 

The PolarFire SoC family is the world’s first SoC FPGA with a RISC-V-based microprocessor subsystem.

The hardened subsystem—which allows users to run Linux or a real-time operating system—is said to bring low-power consumption, thermal efficiency, and defense-grade security to embedded systems.


Microchip PolarFire SoC FPGA

PolarFire SoC FPGA. Image from Microchip

The company states that the new system delivers 30% to 50% total power savings compared to similar devices in the market.

These power-saving metrics are backed by the subsystem's low-power Poly-Si 28nm process, 5-stage in-order CPU, low static power FPGA technology, and power-efficient transceivers. 


Features of the PolarFire SoC Family 

The PolarFire SoC’s CPU has extensive debug capabilities that include instruction trace and passive run-time configurable advanced extensible interface (AXI).

Tim Morin, the director of product marketing in Microchip's PRO business unit, explains that the AXI gives users the ability to figure out who's writing or reading from a memory and when they're doing it.

"It gives me visibility into who's filling up my memory," he comments.

"We also have an AXI bus monitor on the central switch, which controls all the inputs into the fabric, into the IO, into the memory, and into the CPU subsystem. So, I can completely monitor what's going on in these high-bandwidth environments."

The architecture itself is built for reliability and security with features including a single-error correction and double error detection (SEC-DED) on all memories, physical memory protection, differential power analyst (DPA), and 128Kb of flash boot memory. 


PolarFire FPGA Architecture

PolarFire SoC architecture, which includes RISC-V cores and an L2 memory subsystem. Image from Microchip


The PolarFire SoC uses the same transceivers as its FPGA counterpart and offers data rates from 500Mb/s to 12.7Gb/s and broad protocol support.

The PolarFire SoC inherits security features from its PolarFire FPGA predecessor, such as DPA-resistant bitstream programming, true random number generator, and a physically unclonable function.

It also includes added security features, such as physical memory protection, standard secure boot and user-defined secure boot, and Spectre and Meltdown immunity. 


"With Big Data Comes Big Latency"

This launch responds to the market trend toward compute-intensive gateways and edge devices. Edge computing allows data to be handled on a device rather than in the cloud, thereby decreasing latency and power. It's often used in IoT applications for this very reason.

Morin explains that "With big data comes big latency; as things start transitioning to the edge, you start seeing consumer demand and even machine-type demand for lower latency."


Mixed-criticality systems

An L1 memory subsystem is tied locally to the CPU course and an L2 memory subsystem is on-chip to improve performance. Image from Microchip

To accomplish strong computing at the edge, Microchip is offering “real-time to Linux” by creating a chip that runs mainstream Linux OS and all its applications side-by-side with a real-time core.

According to Microchip, including an FPGA and CPU on a single chip allows for improved processing of specific tasks, flexibility, customization, and differentiation.

It is also said to reduce component count, power consumption, and board space. 


PolarFire FPGA's Place Among Competitors

Microchip claims that PolarFire FPGA competes favorably with its competitors that make high-density FPGAs, mid-range FPGAs, and low-density FPGAs. Microchip, however, makes low-density and mid-range FPGAs.


Mid-range FPGA landscape.

Mid-range FPGA landscape. Image from Microchip

"They're coming from the top down we're coming from the bottom up, and there's a distinct advantage of doing that that relates to power," explains Morin.

"We've optimized power in the technology we've chosen—and the design techniques—and we give our customers up to 50% lower power than competing mid-range FPGAs."


The Value of RISC-V

The PolarFire SoC and PolarFire FPGA is a hardened RISC-V processor subsystem. Morin explains the importance of RISC-V as the foundation for both products:

"RISC-V is a clean-slate design. It's simple. It's stable. It's modular. It's extendable. There is a vibrant ecosystem in place. And so, I believe RISC-V helps extend Moore’s law."


RISC-V ecosystem

RISC-V ecosystem. Image from Microchip

Here, he expounds that the ability to create purpose-built CPUs for applications in a low-cost manner, in effect, extends Moore's Law.

Because RISC-V provides an architectural license for free, customers will have a say in the specifics of how Microchip designs products in the future—which Microchip sees as an advantage compared to an "off-the-shelf" piece of IP. 


Target Applications 

With the PolarFire SoC, Microchip looks to provide reliable and secure solutions for the following areas:

  • Thermally-challenged environments, such as industrial IoT switches or remote radio heads
  • Battery-operated environments, such as portable test and measurement equipment and portable ultrasound devices
  • Machine learning focused on inference at the edge
  • Root of Trust, such as with UAVs 


Microchip claims that its non-volatile flash FPGA has no errors.

Microchip claims that its non-volatile flash FPGA prevents errors. Image from Microchip

Microchip also sees this product of use in any low-power systems, space applications, commercial aviation, and defense markets.


Development and Migration Details

Microchip offers a PolarFire SoC development kit that has a PolarFire FPGA and SiFive’s HiFive Unleashed RISC-V CPU on a single board. 

Any designs created for SmartFusion2 can be migrated to PolarFire SoC. The PolarFire SoC includes the ability to configure its 2MB L2 memory as local memory. It also features an 8x increase in application space and a 4x increase in performance compared to the SmartFusion2.

With its EAP, Microchip offers development tools for customers to begin designs.

Microchip will be discussing and demonstrating the new SoC FPGA in more detail at the RISC-V Summit