New PMOS Devices Take a Note on the Low On-Resistance of NMOS

February 12, 2021 by Jake Hertz

Many current P-channel MOSFETs don't cut it for high-voltage applications. To meet the challenge, a new family of PMOS is claimed to feature 62% lower RDS(on) than comparable devices.

While wide-bandgap semiconductors like SiC and GaN are becoming increasingly popular in high-voltage applications like data centers and electric vehicles, silicon FETs are far from forgotten. 


Efficiency vs. switching frequency in silicon, SiC, and GaN

Efficiency vs. switching frequency in silicon, SiC, and GaN. Image used courtesy of Maerz et al. and ResearchGate

Since silicon FETs are still more widely used, designers are demanding higher efficiencies at higher voltages from this technology as well. To address this challenge, ROHM Semiconductor recently announced its 5th-generation P-channel MOSFETs to bring improved performance to high-side switching applications


NMOS vs. PMOS Layout 

The distinction between N-channel (NMOS) and P-channel (PMOS) MOSFETs is relevant to ROHM's announcement because the company is striving to bring some of the strengths of the N-channel MOSFET to this new family of P-channel MOSFETs. 


NMOS and PMOS silicon layouts in a CMOS technology

NMOS and PMOS silicon layouts in CMOS technology. Image used courtesy of Duke University

NMOS and PMOS devices operate on the same principle but can be thought of, in a way, as the inverses of each other. From a silicon-layout perspective, an NMOS consists of two negatively doped n+ wells (for the drain and source) and a positively doped p-type substrate. A PMOS, on the other hand, has two positively doped p+ type wells and a negatively doped n-type substrate. 

NMOS devices feature better efficiencies when used in the high side of a gate voltage—at a higher input voltage than what is necessary. This can make for a complex circuit configuration, however. Alternately, PMOS devices can yield simplified circuit configurations while reducing design load because they can be driven with a gate voltage lower than that of the input voltage. 


Different Layout, Different Operation 

This difference in layout leads to a difference in operation. 

To induce a channel in an NMOS, designers must apply a very positive voltage at the gate relative to the source to create an inversion layer in the channel, allowing for the flow of negative electrons between the drain and source. The PMOS requires the opposite, requiring a low-level voltage at the gate relative to the source and allowing for the flow of positive holes across the channel. 

This phenomenon includes many more complexities than can be encapsulated in a brief explanation. A more comprehensive view of the full operating regions and biasing requirements are shown in the figure below. 


NMOS vs. PMOS operating regions, biasing points, and current equations

NMOS vs. PMOS operating regions, biasing points, and current equations. Image used courtesy of Professor Chang Chip Hong

Besides having to operate with different biasing points, NMOS and PMOS devices have different carrier types (holes vs. electrons). Electrons have significantly higher mobility than holes (two to three times higher), meaning that NMOS devices tend to be more power-efficient with faster switching times and lower RDS(on) values. 


Weak 1s and 0s 

Why even use a PMOS device if they’re slower and less efficient? Sometimes they're the only option; NMOS devices can’t always be used effectively in certain applications. 


NMOS devices pass a “weak 1” when driven with VDD

NMOS devices pass a “weak 1” when driven with VDD. Calculations done by VLSI & MSEE

Because of the biasing point requirements discussed earlier, NMOS devices are not well suited to be used as a pull-up device. For an NMOS to be on, VGS must be greater than Vt. If the drain is connected to VDD (a pull-up configuration) and is being driven with a voltage equivalent to VDD, its source can only reach VGS-VT. This is called passing a “weak 1” since the entire voltage can’t be passed through the device. 

In the same way, PMOS devices pass “weak 0s” and are not suited for pull-down networks.


Complicated Circuitry 

Hence, to use an NMOS device successfully in a pull-up application, designers must drive the gate at a voltage level higher than the input voltage. The problem here, of course, is that this requires complicated extra circuitry including DC-DC converters to generate the extra voltages. Otherwise, one must accept PMOS’ relative inefficiencies.


ROHM’s New Generation of PMOS 

While NMOS will always feature higher-efficiency operation than PMOS, that’s not to say PMOS can't be improved. This seems to be ROHM's intention with its 5th-generation PMOS devices. 

According to ROHM, the new generation comes with both -40 V and -60 V devices, achieving 62% and 52% lower RDS(on) compared to conventional products. These values can be as low as 5.2 milliohms and as high as 78 milliohms. 


ROHM's generation 5 PMOS devices

Application circuits for ROHM's generation 5 PMOS devices. Image used courtesy of ROHM Semiconductor

ROHM claims that these improvements are a result of integrating optimizations in the device structure while simultaneously “adopting a new design that mitigates electric field concentration at the gate trench corner where the electric field is most concentrated.” In this way, the company has been able to improve reliability while minimizing on-resistance. 


Leveling Up Power Management and Industrial Switches

With more efficient PMOS devices, designers face less of a tradeoff between NMOS and PMOS devices in their applications. ROHM envisions the new family being useful for designers working with fan motors and power management switches or industrial switches in industrial or large-scale consumer equipment. This may extend to robotics, AC systems, and factory automation.