Renesas’ New Cortex-M MCUs Break 1 GHz Ceiling for AI Acceleration

Renesas has raised the performance ceiling for general-purpose microcontrollers with the introduction of the RA8P1 group, the company’s first Arm Cortex-M-based MCUs to reach 1 GHz. All About Circuits heard from Daryl Khoo, vice president of embedded processing at Renesas, to learn more about the new MCUs firsthand.

The new MCUs combine Arm Cortex-M85 and M33 cores with an Arm Ethos-U55 NPU to reach reported AI performance benchmarks of up to 256 GOPs.

A First With Cortex-M

One of the major talking points of the new family (datasheet linked) is that the devices integrate a high-performance Cortex-M85 core, optionally combined with a secondary Cortex-M33 running at 250 MHz.

“The Cortex-M33 core available on dual-core MCUs, together with the Cortex-M85, provides over 7,300 CoreMark raw CPU performance for demanding applications,” Khoo said.

Renesas claims that this CoreMark score makes it the highest-performing Cortex-M device on the market to date. The dual-core architecture also lends to system partitioning, where real-time tasks or secure operations are assigned to the M33, while compute-intensive workloads are executed on the M85.

Internal block diagram of the RA8P1. 

The Cortex-M85 supports the M-profile vector extension (MVE) for SIMD acceleration for DSP-style workloads. Its floating-point unit conforms to the IEEE 754-2008 standard for scalar half-, single-, and double-precision operations. Paired with tightly coupled memory regions and 32-KB instruction and data caches, the M85 core sustains high instruction throughput even during concurrent memory and peripheral access.

Renesas combined high CPU frequency and advanced memory architecture to enable the RA8P1 to close the traditional gap between high-end MCUs and low-power MPUs. Developers targeting edge analytics or real-time AI inference can now scale performance while remaining in the familiar MCU toolchain ecosystem, supported by Renesas’ FSP and e2Studio IDE.

Integrated AI Acceleration via Arm Ethos-U55

The RA8P1 integrates the Arm Ethos-U55 neural processing unit (NPU), a specialized inference engine optimized for Cortex-M-class processors. The NPU operates at 500 MHz and delivers 256 GOPS using 256 8 x 8 MACs per cycle and supports 8-bit and 16-bit quantized CNNs and RNNs, including models such as MobileNetV2, DS-CNN, ResNet, and TinyYOLO. In practical benchmarks, inference throughput improved 35x over CPU-only execution.

The RA8P1 integrates an Ethos-U55 NPU. 

The NPU also includes native support for compressed weights and leverages local SRAM and MRAM to minimize latency. Operators not supported in hardware fall back to the Cortex-M85 core so that developers can execute full networks (preprocessing, inference, and postprocessing) within the MCU boundary while avoiding dependence on external co-processors or cloud connectivity.

Process Technology and Embedded MRAM

Another notable feature of the new MCU is that it is fabricated on TSMC’s 22-nm ultra-low leakage (22ULL) process to enable high operating frequencies with minimal static power draw. 

Importantly, 22ULL allows integration of embedded magnetoresistive RAM (MRAM) in place of conventional embedded flash. MRAM offers faster write times, higher endurance, and greater data retention, especially at high temperatures and over extended duty cycles.

“MRAM offers us faster speed and higher retention and endurance than conventional flash memory technology while consuming less power,” Khoo explained.

It also supports byte-level addressability without requiring erase cycles, which simplifies runtime parameter storage and model updates in AI applications. Standard RA8P1 devices include up to 1 MB of on-chip MRAM and 2 MB of ECC-protected SRAM. SiP variants integrate up to 8 MB of external flash through a decryption-on-the-fly (DOTF)-enabled Octal SPI interface.  

Peripheral and Interface Capabilities

The MCU includes an extensive peripheral set optimized for multimodal AI applications. For vision, it supports both MIPI CSI-2 and 16-bit parallel camera interfaces, enabling direct connection to image sensors with frame sizes up to five megapixels. The integrated capture engine unit (CEU) preprocesses incoming frames before memory writeback to reduce software load. A 2D drawing engine and a WXGA-capable LCD controller allow local visualization in HMI applications.

On the audio front, integrated support for PDM microphones and the serial sound interface-enhanced (SSIE) module unlocks stereo digital audio capture and playback with minimal jitter and buffering latency. These interfaces target use cases such as beamforming, keyword spotting, or acoustic anomaly detection.

Communication features include USB 2.0 FS/HS, CAN-FD, SDHI, I3C, and Gigabit Ethernet with a Layer-3 switch and TSN support.  

Blurring MCU and MPU Lines

Renesas asserts that the RA8P1 will shift what microcontrollers can do at the edge. By coupling a 1-GHz Cortex-M85 with a dedicated 256-GOPS NPU on a 22-nm, MRAM-based platform, Renesas has positioned this device as a gateway between the cost and ease of traditional MCU-based systems and the power of AI-capable endpoint computing.

“If we truly want to enable intelligence at the extreme edge and endpoints in the network, it must be done in a way that is highly efficient, responsive in real-time, and cost-effective,” Khoo said.

All images used courtesy of Renesas.