With PowerVia Backside Power, Intel Anticipates Big Chip Breakthroughs
Intel has unveiled a new backside power delivery technology called PowerVia, which decouples power and signal interconnects on a wafer to increase performance and lower costs.
As demand for AI skyrockets, semiconductor manufacturers are seeking new ways to improve the performance of their chips to suit heavy workloads.
While node sizes have shrunk to below 7 nm—even as small as 2 nm—several issues are now playing a critical role in the chip development process. One of these issues is the relationship between signal and power interconnects on a chip. Traditionally, signal and power wires were both on the same side of a silicon wafer. This is known as frontside power delivery.
Precisely manufacturing this complex maze of wires has challenged chipmakers as node sizes have shrunk rapidly over the past decade. In 2021, Imec demonstrated critical building blocks for backside power delivery, claiming increased chip performance while reducing BEOL complexity.
Intel has now introduced PowerVia, its backside power delivery technology. Image (modified) courtesy of Intel
Now, Intel, one of the world's largest chipmakers, presented findings at the 2023 VLSI Symposium indicating its plans to produce chips with backside power delivery as early as next year.
The Benefits of Backside Power Delivery
Backside power delivery offers several benefits to chipmakers. First, it can reduce the amount of lithography expenditure required to manufacture the chip by simplifying the interconnects. As discussed in a recent article on All About Circuits, lithography is the process of patterning a chip onto a semiconductor wafer. For advanced semiconductor device fabrication, extreme ultraviolet (EUV) lithography is used. EUV is very expensive. The machine alone is manufactured by only one company in the world, ASML, and costs over $200 million.
By simplifying and separating the power and signal networks, chipmakers can reduce the complexity of the networks and the photolithography effort. This, in turn, reduces overall chipmaking costs.
Backside power delivery enables significant improvement in IR drop. Image courtesy of IMEC
Additionally, backside power delivery reduces the IR drop within the chip, allowing more power to be delivered to each transistor. As current flows through a wire, the potential (voltage) drops as well. This is known as IR drop.
By using buried power rails and nano-through-silicon-vias (nTSVs), the size of the standard cell is reduced. nTSVs can be constructed through the silicon substrate and are leveraged to reduce standard VLSI cell size. This means the distance that current has to travel is reduced, enabling lower IR drop and more efficient power delivery to the transistors. This also boosts the overall performance of the chip.
Intel to Implement PowerVia in Upcoming 20A and 18A Chips
Intel aims to introduce PowerVia in upcoming chips to maximize transistor density for heavy workloads such as AI and graphics. According to Intel, results from a recent test chip implementing PowerVia have shown 90% cell utilization. Intel says it will implement PowerVia on its 20A (2nm) and 18A (1.8nm) chips, which will also leverage RibbonFET technology.
Power interconnect is separated from the signal interconnect in Intel PowerVia. Image courtesy of Intel via IEEE Sepctrum
RibbonFET allows for a smaller transistor footprint, and Intel seeks to use it in combination with PowerVia to pack more computer power onto a single chip. Intel says it has proved out the PowerVia technology in its latest test chip, Blue Sky Creek. With additional debug capabilities, Intel claims this test chip will demonstrate the reliability and yield of its PowerVia technology.
